FIG. 1 is a configuration diagram of a conventional dynamic comparator 1. The dynamic comparator 1 has two CMOS inverters IV1 and IV2 subject to positive feedback, a differential pair D1 for conducting determination of a magnitude relation between input voltages IN+ and IN−, and a switch M0 for switching on/off of the dynamic comparator 1 depending on a clock signal CLK. The first CMOS inverter IV1 is composed of a PMOS transistor M3 and an NMOS transistor M4 and the second CMOS inverter IV2 is composed of a PMOS transistor M5 and an NMOS transistor M6. The differential pair D1 is composed of an NMOS transistor M1 and an NMOS transistor M2. As the dynamic comparator 1 is turned on by the switch M0, a differential electric current is generated depending on the difference between input voltages IN+ and IN− supplied to the differential pair D1 to cause a difference between the capabilities of the first CMOS inverter IV1 and second CMOS inverter IV2 which are connected as load, whereby it is possible to determine a magnitude relation between input voltages IN+ and IN−.
Additionally, for example, patent document 1 is known as a prior art document for a dynamic comparator.    Patent document 1: Japanese Patent Publication No. 2007-318457